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Janvier 2021
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Archives des actualités


Catégorie : Soutenances de thèse et de HDR

Mercredi 6 janvier 2021 : Soutenance de thèse de Benjamin VIDALES : Architecture de convertisseur intégrant une détection de défauts d'arcs électriques appliquée aux sources d'énergies continues d'origines photovoltaïques

Benjamin VIDALES Doctorant au sein de l'équipe "Mesures et architectures électroniques" de l'Institut Jean Lamour, soutient sa thèse intitulée :

"Architecture de convertisseur intégrant une détection de défauts d'arcs électriques appliquée aux sources d'énergies continues d'origines photovoltaïques"


Date et lieu :
Mercredi 6 janvier 2021 à 15h30

En raison des conditions sanitaires actuelles, la soutenance se déroulera en visio .

Lien de retransmission


Composition du jury :


Directeur de thèse :

- Dr. Serge Weber
Professeur, Institut Jean Lamour, Université de Lorraine, Nancy

Directeur de thèse - Mexique:

- Dr. Manuel Madrigal Martínez
Profesor SNI- II, Tecnológico Nacional de México


Co-directeur de thèse :

-  Dr. Patrick Schweitzer
MCU – HDR, Institut Jean Lamour, Université de Lorraine, Nancy

Co-directeur de thèse - Mexique:

- Dr. Domingo Torres LucioProfesor, Tecnológico Nacional de México


- Dr. Bertrand Raison
Professeur, Université de Grenoble Alpes, Grenoble

- Dr. El-Hassane Aglzim
Professeur, Université de Bourgogne, Nevers

- Dr. Erwan Carvou
Ingénieur de recherche - HDR, Université de Rennes1, Rennes


- Dra. Nadia Maria Salgado Herrera
Profesora Asociada, Instituto de Energías Renovables (IER -Mexique)


Invité :

- Dr. José Luis Monroy-Morales
Profesor SNI- C, Tecnológico Nacional de México


Abstract :
In this research work, the development of a multilevel inverter for PV applications is presented. The PV inverter, has two stages one DC/DC converter and one DC/AC inverter, and is capable of generating an AC multilevel output of nine levels, it's a transformerless inverter and uses a reduced number of components compared to other topologies. The conception of a novel DC/DC converter is capable of generating two isolated DC voltage levels needed to feed the DC/AC stage. This DC/DC stage is developed in two variants, buck and boost, the \u001Crst to perform the reduction of voltage when the DC bus is too high, and second to increase the voltage when the DC bus is too low to perform interconnection with the grid through the DC/AC inverter.

This is achieved thanks to the parallel functioning of the developed topology, which make use of moderated duty cycles, that reduces the stress in the passive and switching components, reducing potential losses. The validation of the PV inverter is performed in simulation and experimental scenarios. In the other hand, the response of the inverter facing an arc fault in the DC bus is studied by performing a series of tests where the fault is generated in strategic points of the DC side, this is possible thanks to the design and construction of an arc fault generator based in the speci\u001Ccations of the UL1699B norm.

During the tests is observed that with the apparition of an arc fault, there is a lost in the half-wave symmetry of the AC multilevel output voltage waveform, generating even harmonics which aren't present during normal operation, only when an arc fault is present in the DC system. The monitoring of even harmonics set the direction for developing the detection technique. Since the magnitude of even harmonics in the inverter is very low, the total even harmonic distortion is employed as a base for the detection technique presented in this thesis. The e\u001Bectiveness of this method is veri\u001Ced with a series of tests performed with di\u001Berent loads.